There is currently much interest in developing thin-film circuits with TFTs on glass and on other inexpensive insulating substrates for large area electronics applications. Such TFTs fabricated with amorphous or polycrystalline semiconductor films may form the switching elements of a cell matrix, for example in a flat panel display as described in U.S. Pat. No. 5,130,829 (our reference PHB33646), the whole contents of which are hereby incorporated herein as reference material. A recent development involves the fabrication and integration of circuits from TFTs (often using polycrystalline silicon) as, for example, integrated drive circuits for such a cell matrix. In order to increase the circuit speed, it is advantageous to avoid an overlap of the TFT gate with its source and drain. Therefore preferably a self-alignment process is used at this stage in the manufacture.
Published Japanese Patent Application Kokai JP-A-63-47981 describes the manufacture of a TFT on a substrate, the transistor having a gate for controlling current flow between source and drain, and the gate being formed using self-aligned photolithographic process steps which include:
(a) selectively exposing a first photoresist film by illumination through the substrate while using opaque areas of the source and drain as a photomask, and PA1 (b) developing the selectively-exposed first photoresist film to leave a first photoresist area for defining an area of the gate. PA1 (a) selectively exposing a first photoresist film by illumination through the substrate while using opaque areas of the source and drain as photomask, and PA1 (b) developing the selectively-exposed first photoresist film to leave a first photoresist area for defining an area of the gate, which method is characterised in that the transistor has first and second gates formed from respective first and second conductive layers in separate self-aligned photolithographic process steps, wherein the first photoresist film of steps (a) and (b) is of the positive type and is used in a lift-off process including the steps of: PA1 (c) depositing the first conductive layer of opaque material after developing the first photoresist film in step (b), and PA1 (d) then removing the first photoresist area to leave a first area of the first conductive layer where the first and second gates are to be provided, after which a part of the first area of the first conductive layer is removed in a step (e) to leave a smaller, second area of the first conductive layer for forming the first gate, and thereafter the second photoresist film is provided in a step (f), and the second gate is then formed by further self-aligned photolithographic process steps which include: PA1 (g) selectively exposing the second photoresist film by illumination through the substrate while using the opaque areas of the source and drain and first gate as a photomask, and PA1 (h) developing the selectively-exposed second photoresist film to leave a second photoresist area for defining an area of the second conductive layer which provides the second gate.
JP-A-63-47981 acknowledges that a lift-off process was known (e.g. as illustrated in FIG. 8 of JP-A-63-47981) using a photoresist of the positive type which is exposed and developed before depositing a conductive layer for the gate. JP-A-63-47981 considers that the lift-off process has a poor yield and teaches avoiding such a lift-off process by forming the gate from a transparent conductive layer with a negative-type photoresist in steps (a) and (b); the transparent conductive film is deposited before providing this negative-type photoresist film for step (a). The photoresist area left on the transparent conductive layer after development is used subsequently as an etchant mask while etching away the conductive layer from over the source and drain; the remaining unetched area of the conductive film forms the gate. The whole contents of JP-A-63-47981 are hereby incorporated herein as reference material.
However the present inventor has found such an approach imposes undesirable restrictions and constraints on the types of gate structure which can be formed using self-aligned photolithographic process steps, and particularly in the case of a TFT having more than one gate.